A random access memory (RAM) utilizing a magnetoresistive effect, in which a resistance value varies depending on a magnetic orientation, is drawing attention recently. Such a RAM utilizing the magnetoresistive effect is referred to as a magnetoresistive RAM (MRAM). Magnetoresistive effects includes an anisotropic magnetoresistive (AMR) effect, a giant magnetoresistive (GMR) effect, and the like are known. In particular, a tunnel magnetoresistive (TMR) effect, which gains a magnetoresistive effect by use of a tunneling current, is highlighted for capability of gaining large magnetic-field sensitivity.
A spin-valve element using the TMR has a laminated structure including an antiferromagnetic layer, a ferromagnetic layer (a pinned layer), an insulating layer (a tunnel layer), and another ferromagnetic layer (a free layer). Such a spin-valve element is also referred to as a magnetic tunnel junction (MTJ) element. The antiferromagnetic layer has a function to fix a magnetic orientation of the adjacent ferromagnetic layer (the pinned layer), whereby a tunneling current flows in the insulating layer when the magnetic orientation of the free layer coincides with the magnetic orientation of the pinned layer. On the contrary, when the magnetic orientation of the free layer is made reverse to the magnetic orientation of the pinned layer, an electric current flowing in the insulating layer becomes less than the tunnel current in the coincided case. In other words, a resistance value of the MTJ element in the direction of lamination varies depending on the magnetic orientation (an orientation of electronic spin) of the free layer. Information regarding “0” or “1” is recordable depending on the magnetic orientation of the free layer, whereby a memory element for retrieving the information in accordance with variation of the resistance value of the MTJ element can be constituted.
As it is clear from the foregoing principle, the memory element (the MRAM) using the TMR effect is nonvolatile; therefore, the memory element constitutes a static element which does not cause destruction of a recorded content upon retrieval of the information. Moreover, retrieval of the information is conducted only by detecting resistance variation of the MTJ element. Therefore, only one switching element, such as a select transistor, is required in a primitive cell for recording one bit. Accordingly, the MRAM is expected to achieve integration as dense as a dynamic random access memory (DRAM) (i.e. low-cost), and to realize a nonvolatile memory such as an electrically erasable read only memory (EEPROM). In addition, it is possible to constitute a memory without causing soft errors or errors attributable to high-energy rays such as cosmic rays as in a static random access memory (SRAM). Moreover, it is possible to realize a solid-state memory element which does not require refreshing as in the DRAM. Furthermore, the MRAM does not have limitation of the number of rewriting as in the EEPROM, and a rewriting speed is also considerably faster than the EEPROM. Due to the numerous and remarkable advantages as described above, the MRAM is expected to be one of the most promising memory devices to replace conventional solid-state memories.
A typical MRAM memory cell structure includes the 1MTJ+1Tr (one MTJ element and one transistor) constitution as described above. Nevertheless, retrieval of the information out of the MRAM cell is based on variation of the resistance value (or voltage variation in the case of constant-current drive). Accordingly, if it is possible to apply a reverse bias between a sense line and a word line of an unselected cell, then a diode can substitute for the switching element. Moreover, writing the information can be achieved by application of an electric current to a word line and a sense line of a selected cell intersecting each other. Therefore, any special function is not required in the switching element. Accordingly, conceivable is a technology of using a diode as the switching element. By use of a diode, the switching element can be formed with a smaller occupied area than forming a transistor (a field effect transistor: FET). Accordingly, it is possible to further enhance the advantage of the MRAM, which is to achieve integration as dense as the DRAM. Moreover, it is not necessary to provide a gate electrode (which function as a readout control line) for controlling on/off states of a select transistor, and a word line (or a bit line) for reading and a word line (or a bit line) for writing can be combined into one line.
For example, U.S. Pat. No. 5,640,363 (Document 1) discloses a memory cell of a stacked structure, in which a thin-film diode of a thin-film transistor (TFT) type is adopted as a switching element and the thin-film diode and an MTJ element is stacked vertically. The memory cell is constituted by sandwiching the stacked structure of the diode and the MTJ element between a word line and a bit line (a sense line) mutually intersecting each other, and a resistance value (or a voltage value in the case of constant-current drive) between the word line and the bit line is measured in order to retrieve information. Upon writing the information, an electric current is applied to a word line and a bit line (a sense line) intersecting in a position of a selected cell, whereby information is written with a composite magnetic field generated therein. A minimum occupied area of the memory cell structure is defined by a necessary current density or a minimum processing dimension required in the MTJ element or in the thin-film diode. Accordingly, the memory cell structure can constitute an MRAM memory cell with the smallest occupied area theoretically.
Nevertheless, the memory cell structure disclosed in Document 1 involves numerous problems. Firstly, the thin-film diode has difficulty in gaining a required on/off ratio. Whereas an on/off ratio of about four digits is preferred, the current thin-film diode cannot gain such an on/off performance easily. Secondly, there is a problem of flatness of a substrate required in the MTJ element. Since magnetic layers and a tunnel insulating film of the MTJ element are formed into extremely thin films, atomic-level flatness is required in the substrate for the MTJ element. Nevertheless, it is difficult for the thin-film diode to achieve such atomic-level flatness, because the thin-film diode is generally made of a polycrystalline silicon film. Accordingly, it is extremely difficult to stack the MTJ element having a predetermined characteristic onto the thin-film diode. Thirdly, on-state resistance of the thin-film diode incurs a problem along with downsizing of the MTJ element. Although there is growing possibility for downsizing the MTJ element in line with characteristic improvements thereof, it is not possible to reduce the on-state resistance of the thin-film diode relevantly to such a downsizing level.
Due to existence of the foregoing disadvantages, it is currently conceived difficult to realize the memory cell structure of stacking the MTJ element on the thin-film diode. In this context, another memory cell structure is proposed, in which a diode is formed on a surface of a semiconductor substrate. For example, U.S. Pat. No. 6,097,625 (Document 2) discloses a memory cell structure, in which a pn-junction diode is constituted by forming an n+ diffusion layer and a p+ diffusion layer on a surface of a semiconductor substrate (a silicon wafer) and an MTJ element is disposed on a region where the junction diode is formed. A word line to be connected to the n+ diffusion layer of the diode is disposed on an insulating film on the substrate, and a sense line is disposed above the word line so as to extend in a direction orthogonal to an extending direction of the word line. The MTJ element is disposed so as to be sandwiched in an intersecting region of the word line and the sense line. One end of the MTJ element contacts with the sense line, and the other end thereof is connected to the p+ diffusion layer via a conductive member such as local wiring. In short, the diode and the MTJ element are serially connected between the sense line and the word line. As similar to the stacked structure disclosed in Document 1, it is possible to retrieve information by measuring a resistance value (or a voltage value) between the word line and the sense line, and to write the information by applying an electric current to the word line and the sense line intersecting each other in a position of a selected cell. In this structure, a sufficient on/off ratio can be obtained because the diode is formed on the surface of the semiconductor substrate. Moreover, it is also possible to reduce on-state resistance because a sufficiently large pn-junction area can be secured. Furthermore, since the MTJ element is formed on an insulating film and on a metallic film where sufficient flatness can be secured, disadvantages as cited in the case of the thin-film diode do not exist therein.
Nevertheless, the memory cell disclosed in Document 2 also involves the following problems. Specifically, since the junction diode is formed on the semiconductor substrate or on a well structure, the diode and the well (or the semiconductor substrate) collectively constitutes a vertical bipolar transistor, which is so-called a parasitic transistor. Depending on aspects of biasing the memory cell, there may be a case where the parasitic transistor starts functioning and a memory cell operation cannot be secured as intended at a designing stage. Moreover, Document 2 also discloses a constitution of a gated diode, in which an FET is formed on the semiconductor substrate, and a diode is formed between a gate of this FET and either a source or a drain thereof. However, the memory cell composed of the gated diode and the MTJ element cannot fulfill a small occupied area. Therefore, the memory cell is disadvantageous to downsizing.